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.obsidian/workspace.json
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.obsidian/workspace.json
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1
Semester 7/REDIG/VHDL-Typeconversion.md
Normal file
1
Semester 7/REDIG/VHDL-Typeconversion.md
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Entwerfen Sie eine **synchrone Schaltung** mit **variabler Bitbreite**. Die Schaltung besitzt die Eingänge *clk_i*, *reset_i* und *en_i* vom **Typ std_logic** sowie den Eingang *startwert_i* und den Ausgang *zaehler_o* vom **Typ unsigned(n downto 0)**. Zusätzlich besitzt die Schaltung den Ausgang *overflow_o* vom **Typ std_logic**. Die Bitbreite wird über den **generischen Parameter n** vorgegeben. Die Schaltung arbeitet vollständig **synchron** zur **steigenden Flanke des Systemtakts**. Bei jeder steigenden Taktflanke wird der am Ausgang anliegende Zählerwert genau dann um eins erhöht, wenn en_i den Wert '1' hat. Wenn en_i den Wert '0' hat, muss der Zählerwert unverändert bleiben. Der Rücksetzeingang ist aktiv bei '1' und lädt den Zählerwert synchron zur steigenden Taktflanke mit dem momentan anliegenden Wert von startwert_i. Der Ausgang overflow_o muss in jedem Takt standardmäßig den Wert '0' haben und darf nur dann für genau einen Takt den Wert '1' annehmen, wenn der Zähler bei einer steigenden Taktflanke von seinem Maximalwert (alle Bits '1') auf den Wert 0 übergeht. Der Überlaufimpuls soll also genau in dem Takt auftreten, in dem der Überlauf geschieht. Wenn en_i den Wert '0' hat, darf overflow_o nicht ausgelöst werden. Wenn der Zähler im laufenden Betrieb den Wert 0 erreicht oder irgendeinen anderen Wert hat, passiert außer dem beschriebenen Hochzählen nichts Besonderes. Änderungen von en_i oder startwert_i innerhalb einer Taktperiode dürfen keinen Einfluss auf die Ausgänge haben; es zählt ausschließlich der Wert zur steigenden Taktflanke. Das Entity soll den Namen aufgabe2 tragen. Für das Bestehen der Aufgabe muss die Schaltung die vorgegebene Testbench aufgabe2Tb vollständig bestehen. Es ist nicht zulässig, die Testbench zu verändern.
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