vault backup: 2025-10-20 11:41:41

This commit is contained in:
fzzinchemical
2025-10-20 11:41:41 +02:00
parent 27943bf82a
commit b1219f8e78
3 changed files with 42 additions and 64 deletions

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@@ -13,12 +13,12 @@
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@@ -0,0 +1,37 @@
# VHDL
Basis 3 Board oder Basis 2 Board
Vivado wird im Labor verwendet, installationsvorgaben sind in Aulis vorzufinden
In der Übung heute VHDL ausprobieren
folgende List ist nicht vollständig und repräsentiert nur das durch Herrn Bredereke präsentierte Projekt ()
## Typen
- character
- string
- integer
## Datenformate
`type <name> is (a, b, c);`
`type <name> is array();`
`type <name> is record ... end record;`
`constant <name>: <type> := <value>`
## Schnittstellen
```vhdl
entity <name> is
port();
end <name>;
```
## Objekte
``` vhdl
constant <name>: <type> := ();
```
## Zuweisung
```vhdl
constant <name>: integer := 0 --deklaration
<name> <= 1 --variabeländerung
```